Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
TABLE 1: Output Signals SKEW Programming Summary:
Bit<2:0>
111
110
101
100
011
010
001
000
DDR Skew Setting (± 100ps/step)
±
+400ps
+300ps
+200ps
+100ps
Default
-100ps
-200ps
-300ps
Setting applies to the following
outputs:
1. DDRA: CLK0, CLK1, CLK5
2. DDRB: CLK2, CLK3, CLK4.
FBOUT Skew Setting (± 200ps/step)
±
+800ps
+600ps
+400ps
+200ps
Default
-200ps
-400ps
-600ps
Setting applies to the following out-
puts:
1. FB_OUTT
3. BYTE 6: SKEW Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Skew
DDRA
-
Name
-
-
Bit <2>
Bit <1>
Bit <0>
-
-
-
Default
-
-
0
1
1
-
-
-
Reserved
Reserved
Description
These three bits will adjust timing of DDRA signals (CLK0, CLK1,
CLK5) either positive or negative delay up to +400ps or –300ps
with
±100ps
per step. (see Table 1)
Reserved
Reserved
Reserved
-
-
4. BYTE 7: SKEW Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DDR-SKEWEN
FBOUT-SKEWEN
Skew
DDRC
-
Bit <2>
Bit <1>
Bit <0>
-
-
-
Default
1
1
0
1
1
-
-
-
1= disable, 0= enable
1= disable, 0= enable
Description
These three bits will adjust timing of DDRC signals (CLK2, CLK3,
CLK4) either positive or negative delay up to +400ps or –300ps
with
±100ps
per step. (see Table 1)
Reserved
Reserved
Reserved
Rev 02/26/03 Page 4
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47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
PLL [ PHASELINK CORPORATION ]
