PLL650-02
Low EMI Network LAN Clock
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications
PARAMETERS
Input Frequency
Output Rise Time
Output Fall Time
Duty Cycle*
Max. Absolute Jitter
Max. Jitter, cycle to cycle
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At V
DD
/2
Short term
45
50
±150
80
CONDITIONS
MIN.
10
TYP.
25
MAX.
27
1.5
1.5
55
UNITS
MHz
ns
ns
%
ps
ps
* : in case SDRAM output is selected to be 83.3MHz, the duty cycle of output pin 22 will be 40%-60% if its output frequency is selected to be 100MHz
(FS2=1). In all other situations, pin 22 will also have a 50%-50% typical duty cycle.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 4
PLL [ PHASELINK CORPORATION ]
