PLL650-02
Low EMI Network LAN Clock
3. DC Specifications
PARAMETERS
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage At
CMOS Level
Operating Supply Current
Short-circuit Current
Nominal output current*
Nominal output current*
Internal pull-up resistor
Internal pull-up resistor
SYMBOL
V
DD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
I
DD
I
S
I
out
I
out
R
up
R
up
CONDITIONS
MIN.
2.97
TYP.
V
DD
/2
V
DD
/2
MAX.
3.63
V
DD
/2 - 1
0.5
UNITS
V
V
V
V
V
V
V
V
V
V
For all Tri-level input
For all Tri-level input
For all normal input
For all normal input
I
OH
= -25mA
I
OL
= 25mA
I
OH
= -8mA
No Load
V
DD
-0.5
2
0.8
2.4
0.4
V
DD
-0.4
35
±100
mA
mA
mA
mA
kΩ
kΩ
CMOS output level
TTL output level
Pins 6,8
Pin 3
35
20
40
25
60
120
*: SDRAM output strengths are doubled (i.e. min. CMOS level is 70mA, typ. CMOS level is 80mA)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 5
PLL [ PHASELINK CORPORATION ]
