RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Figure 10 – GPIC Address Map
PCI ADDRESS MAP
0B
CBI Registers
Base Address
CBI Registers
8KB
4GB
The GPIC responds with medium timing to master accesses. (i.e. DEVSELB is
asserted 2 PCICLK cycles after FRAMEB asserted). The GPIC inserts five wait
states on reads to the internal CBI register space (six wait states for the 2nd and
subsequent dwords of a burst read). The target machine will only terminate an
access with a Retry if the target is locked and another master tries to access the
GPIC. The GPIC will terminate any access to a non-burst area with a
Disconnect and always with data transferred. The target does not support
delayed transactions. The GPIC will perform a Target-Abort termination only in
the case of an address parity error in an address that the GPIC claims.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
60
PMC [ PMC-SIERRA, INC ]
