RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
and the packet status information associated with the data in each buffer. TDs
are transferred from the TMAC256 to the host and vice versa using descriptor
reference queues. The TMAC256 maintains all the pointers for the operation of
the queues. The TMAC256 acquires buffers with data ready for transmission by
reading TDRs from a TDR ready queue. After a packet has been transmitted,
the TMAC256 places the associated TDR onto a TDR free queue.
To minimise host bus accesses, the TMAC256 maintains a descriptor reference
table to store current DMA information. This table contains separate DMA
information entries for up to 256 transmit channels. The TMAC256 also
performs per-channel sorting of packets received in the TDR ready queue to
eliminate head-of-line blocking.
8.7.1 Data Structures
The TMAC256 communicates with the host using Transmit Descriptors (TD),
Transmit Descriptor References (TDR), the Transmit Data Reference Ready
(TDRR) queue and the Transmit Data Reference Free (TDRF) queue.
The TMAC256 reads packet data from data buffers in host memory. The TD,
TDR, TDRR queue, and TDRF queue are data structures which are used to
transfer host memory data buffer information. All four data structures are
manipulated by both the TMAC256 and the host computer. The TD holds the
data buffer size, data buffer address, and other packet information. The TDR is
a pointer which is used to index into a table of TDs. The TDRR queue and TDRF
queue allow the TMAC256 and the host to pass TDRs back and forth. These
data structures are described in more detail in the following sections.
Transmit Descriptor
The Transmit Descriptors (TDs) pass buffer and packet information between the
TMAC256 and the host. Both the TMAC256 and the host read and write
information in the TDs. TDs are stored in host memory in a Transmit Descriptor
Table. The Transmit Descriptor structure is shown in Figure 11.
Figure 11 – Transmit Descriptor
Bit 31
Data Buf fer Start Address [31:0]
Bytes In Buffer [15:0]
V
TM AC Next TD P ointer[14:0]
Reserved (16)
P AB T IOC CE Res (2)
M
TCC[9:0]
0
H ost Next TD P ointer[14 :0]
Transm it Buf fer Size[15:0]
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