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PM7384-BI 参数 Datasheet PDF下载

PM7384-BI图片预览
型号: PM7384-BI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理84P672 [FRAME ENGINE AND DATA LINK MANAGER 84P672]
分类和应用:
文件页数/大小: 358 页 / 2808 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Figure 25 – Receive Link Timing
RCLK[n]
RD[n]
14.4 Transmit Link Timing
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals is
shown in Figure 26. The transmit data is viewed as a contiguous serial stream.
There is no concept of time-slots or framing. Every eight bits are grouped
together into a byte with arbitrary byte alignment. Octet data is transmitted from
most significant bit (B1 in Figure 26) and ending with the least significant bit (B8
in Figure 26). Bits are updated on the falling edge of TCLK[n]. A transmit link
may be stalled by holding the corresponding TCLK[n] quiescent. In Figure 26,
bits B5 and B2 are shown to be stalled for one cycle while bit B6 is shown to be
stalled for three cycles. In Figure 26, the quiescent period is shown to be a low
level on TCLK[n]. A high level, effected by extending the high phase of the
previous valid bit, is also acceptable. Gapping of TCLK[n] can occur arbitrarily
without regard to byte nor frame boundaries.
Figure 26 – Transmit Link Timing
TCLK[n]
TD[n]
14.5 PCI Interface
B1 B2 B3 B4
B5
B6
B7 B8 B1
B2
A PCI burst read cycle is shown In Figure 27. The cycle is valid for target and
initiator accesses. The target is responsible for incrementing the address during
the data burst. The 'T' symbol stands for a turn around cycle. A turn around
cycle is required on all signals which can be driven by more than one agent.
During Clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It
also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines
with the read command. In the example below, the command would indicate a
burst read. The IRDYB, TRDYB and DEVSELB signals are in turnaround mode
(i.e. no agent is driving the signals for this clock cycle). This cycle on the PCI
bus is called the address phase.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
323