PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
14.2 SBI ADD BUS Interface Timing
Figure 24 – DS3 Add Bus Adjustment Request Functional Timing
REFCLK
C1FP
ADATA[7:0]
APL
AV5
ADP
AJUST_REQ
AACTIVE
C1
···
···
···
···
···
···
···
···
H3
H3
H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
negative justification requests as an example. (The responses to the justification
requests would take effect during the next multi-frame.) The negative
justification request occurs on the DS-3#3 tributary when AJUST_REQ is
asserted high during the H3 octet. The positive justification occurs on the DS-3#2
tributary when AJUST_REQ is asserted high during the first DS-3#2 octet after
the H3 octet. The AACTIVE signal is shown for the case in which FREEDM-
84P672 is only driving DS-3#2 onto the SBI ADD bus.
14.3 Receive Link Timing
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals is
shown in Figure 25. The receive data is viewed as a contiguous serial stream.
There is no concept of time-slots or framing. Every eight bits are grouped
together into a byte with arbitrary alignment. The first bit received (B1 in Figure
25) is deemed the most significant bit of an octet. The last bit received (B8) is
deemed the least significant bit. Bits that are to be processed by the FREEDM-
84P672 are clocked in on the rising edge of RCLK[n]. Bits that should be
ignored (X in Figure 25) are squelched by holding RCLK[n] quiescent. In Figure
25, the quiescent period is shown to be a low level on RCLK[n]. A high level,
effected by extending the high phase of the previous valid bit, is also acceptable.
Selection of bits for processing is arbitrary and is not subject to any byte
alignment nor frame boundary considerations.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
322
PMC [ PMC-SIERRA, INC ]
