PO100HSTL11A
1 to 2 Differential Clock/Data Fanout Buffer
2.4V -3.6V Differential inputs to HSTL outputs Clock Buffer
02/11/07
FEATURES:
• Patented Technology
• Two HSTL differential outputs
• One pair of LVDS/LVPECL/HSTL/ differential
or single-ended inputs
• Operating frequency up to 1.24GHz with 2pf load
• Operating frequency up to 900MHz with 5pf load
• Operating frequency up to 400MHz with 15pf load
• Very low output pin to pin skew < 40ps
• Propagation delay < 2.0ns max with 15pf load
• 2.4V to 3.6V power supply
• Industrial temperature range: –40°C to 85°C
• Available in 8-pin SOIC package
• Available in 8-pin TSSOP package
DESCRIPTION:
Potato Semiconductor’s PO100HSTL11A is
designed for world top performance using
submicron CMOS technology to achieve 1.24GHz
HSTL output frequency with less than 2.0ns
propagation delay.
The
PO100HSTL11A
is a low-skew, 1-to-2
differential fanout buffer targeted to meet the
requirements of high-performance clock and data
distribution applications. The device has a fully
differential internal architecture that is optimized
to achieve low signal skews at operating frequen-
cies of up to 1.24GHz .
Pin Configuration
Logic Block Diagram
Q0
Q0
Q0
Q1
Q1
1
2
3
4
8
7
6
5
Vcc
D
Q0
D
D
GND
D
Q1
Q1
Pin Description
PIN
D, D
Q0, Q0, Q1, Q1
V
CC
GND
FUNCTION
LVDS LVPECL HSTL Inputs
HSTL Outputs
Positive Supply
Ground Supply
1
Copyright
© Potato Semiconductor Corporation
POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
