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PO74G112A 参数 Datasheet PDF下载

PO74G112A图片预览
型号: PO74G112A
PDF下载: 下载PDF文件 查看货源
内容描述: 双负边沿触发的JK触发器具有清零和预设 [DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET]
分类和应用: 触发器
文件页数/大小: 6 页 / 579 K
品牌: POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
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PO74G112A  
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP  
WITH CLEAR AND PRESET  
04/19/09  
74 Series GHz Logic  
Power Supply Characteristics  
Symbol  
IccQ  
Description  
Test Conditions (1)  
Vcc=Max, Vin=Vcc or GND  
Min  
Typ  
Max Unit  
Quiescent Power Supply Current  
-
0.1  
40  
uA  
Notes:  
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at Vcc = 3.3V, 25°C ambient.  
3. This parameter is guaranteed but not tested.  
4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.  
Capacitance  
Parameters (1)  
Cin  
Description  
Test Conditions  
Vin = 0V  
Typ  
Unit  
pF  
Input Capacitance  
Output Capacitance  
4
6
Cout  
Vout = 0V  
pF  
Notes:  
1 This parameter is determined by device characterization but not production tested.  
Switching Characteristics  
Symbol  
tsu  
Description  
Test Conditions (1)  
Max  
-
-
Min  
0.5  
0.5  
-
-
-
Unit  
ns  
Setup time before CLK  
Hold time, data after CLK  
Propagation Delay CLK to Q  
th  
ns  
CL = 15pF  
CL = 15pF  
PLH  
PHL  
2
ns  
ns  
ns  
t
t
Propagation Delay CLK to Q  
Rise/Fall Time  
2
0.8V – 2.0V  
CL=2pF - 15pF  
tr/tf  
0.8  
-
Input Frequency  
fmax  
MHz  
750  
Notes:  
1. See test circuits and waveforms.  
2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested.  
3. Airflow of 1m/s is recommended for frequencies above 500MHz  
3
Copyright © Potato Semiconductor Corporation