PE64907
Product Specification
Serial Interface Operation and Sharing
The PE64907 is controlled by a three wire SPI-
compatible interface with enable active high. As
shown in
Figure 10,
the serial master initiates the
start of a telegram by driving the SEN (Serial
Enable) line high. Each bit of the 8-bit telegram
(MSB first in) is clocked in on the rising edge of
SCL (Serial Clock), as shown in
Table 5
and
Figure 10.
Transitions on SDA (Serial Data) are
allowed on the falling edge of SCL. The DTC
activates the data on the falling edge of SEN. The
DTC does not count how many bits are clocked and
only maintains the last 8 bits it received.
Figure 10. Serial Interface Timing Diagram
t
EOW
t
ESU
t
DSU
t
DHD
t
R
t
F
t
SCL
t
SCLH
t
SCLL
t
EHD
More than 1 DTC can be controlled by one interface
by utilizing a dedicated enable (SEN) line for each
DTC. SDA, SCL, and V
DD
lines may be shared as
shown in
Figure 11.
Dedicated SEN lines act as a
chip select such that each DTC will only respond to
serial transactions intended for them. This makes
each DTC change states sequentially as they are
programmed.
Alternatively, a dedicated SDA line with common
SEN can be used. This allows all DTCs to change
states simultaneously, but requires all DTCs to be
programmed even if the state is not changed.
SEN
SCL
SDA
b0
b7
b6
b5
b4
b3
b2
b1
b0
DTC Data
D
m-2
<7:0>
D
m-1
<7:0>
D
m
<7:0>
Table 5. 8-Bit Serial Programming Register Map
b7
0
1
Figure 11. Recommended Bus Sharing
RF+
V
DD
SDA
SCL
SEN1
SEN2
V
DD
SDA
SCL
SEN
GND
RF-
b6
0
1
b5
STB
2
b4
d4
b3
d3
b2
d2
b1
d1
b0
d0
DTC 1
MSB (first in)
LSB (last in)
Notes: 1. These bits are reserved and must be written to 0 for proper operation
2. The DTC is active when low (set to 0) and in low-current stand-by
mode when high (set to 1)
Table 6. Serial Interface Timing Characteristics
V
DD
= 2.75V, -40 °C < T
A
< +85 °C, unless otherwise specified
Symbol
t
SCL
t
SCLL
t
SCLH
t
R
t
F
t
ESU
t
EHD
t
DSU
t
DHD
t
EOW
Parameter
Serial Clock Period
SCL Low Time
SCL High Time
SCL, SDA, SEN Rise Time
SCL, SDA, SEN Fall Time
SEN rising edge to SCL rising edge
SCL rising edge to SEN falling edge
SDA valid to SCL rising edge
SDA valid after SCL rising edge
SEN falling edge to SEN rising edge
19.2
19.2
13.2
13.2
38.4
Min
38.4
13.2
13.2
6.5
6.5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RF+
V
DD
SDA
SCL
SEN
GND
RF-
DTC 2
Document No. DOC-30214-2
│
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