欢迎访问ic37.com |
会员登录 免费注册
发布采购

ASM5P2305AG-1-08-TR 参数 Datasheet PDF下载

ASM5P2305AG-1-08-TR图片预览
型号: ASM5P2305AG-1-08-TR
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V零延迟缓冲器 [3.3V Zero Delay Buffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 19 页 / 374 K
品牌: PULSECORE [ PulseCore Semiconductor ]
 浏览型号ASM5P2305AG-1-08-TR的Datasheet PDF文件第5页浏览型号ASM5P2305AG-1-08-TR的Datasheet PDF文件第6页浏览型号ASM5P2305AG-1-08-TR的Datasheet PDF文件第7页浏览型号ASM5P2305AG-1-08-TR的Datasheet PDF文件第8页浏览型号ASM5P2305AG-1-08-TR的Datasheet PDF文件第10页浏览型号ASM5P2305AG-1-08-TR的Datasheet PDF文件第11页浏览型号ASM5P2305AG-1-08-TR的Datasheet PDF文件第12页浏览型号ASM5P2305AG-1-08-TR的Datasheet PDF文件第13页  
October 2006
rev 2.2
ASM5P2305A
ASM5P2309A
Switching Characteristics for ASM5I2305A-1H and ASM5I2309A-1H - Industrial Temperature Devices
13
Parameter
1/t
1
Description
Output Frequency
Duty Cycle
12
Test Conditions
30pF load
10pF load
Measured at 1.4V, F
OUT
< 50.0MHz
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins
of the device
Measured between 0.8V and 2.0V using Test
Circuit #2
Measured at 66.67MHz, loaded outputs
Stable power supply, valid clock presented on
REF pin
Min
15
15
40
45
Typ
Max
100
133
Unit
MHz
%
nS
nS
pS
pS
pS
V/nS
= (t
2
/ t
1
) * 100 Measured at 1.4V, F
OUT
= 66.67MHz
50
50
60
55
1.5
1.5
250
Duty Cycle
12
= (t
2
/ t
1
) * 100
t
3
t
4
t
5
t
6
t
7
t
8
t
J
t
LOCK
Notes:
Output Rise Time
12
Output Fall Time
12
Output-to-output skew
12
Delay, REF Rising Edge to
CLKOUT Rising Edge
12
0
0
1
± 350
700
Device-to-Device Skew
12
Output Slew Rate
12
Cycle-to-cycle jitter
12
PLL Lock Time
12
200
1.0
pS
mS
12. Parameter is guaranteed by design and characterization. Not 100% tested in production
13. All parameters specified with loaded outputs.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
9 of 19