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ASM5P23S08AF-3-16-TR 参数 Datasheet PDF下载

ASM5P23S08AF-3-16-TR图片预览
型号: ASM5P23S08AF-3-16-TR
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V “ SpreadTrak ”零延迟缓冲器 [3.3V ‘SpreadTrak’ Zero Delay Buffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 17 页 / 385 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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November 2006
rev 1.5
Switching Characteristics for ASM5I23S08 Industrial Temperature Devices
Parameter
1/t
1
1/t
1
1/t
1
Description
Output Frequency
Output Frequency
Output Frequency
Duty Cycle = (t
2
/ t
1
) * 100
( -2, -3, -4, -1H, -5H)
Duty Cycle = (t
2
/ t
1
) * 100
( -2, -3, -4, -1H, -5H)
t
3
t
3
t
3
t
4
t
4
t
4
Output Rise Time ( -2, -3, -4)
Output Rise Time
11
11
11
11
ASM5P23S08A
Test Conditions
30pF load, All devices
20pF load, -5H devices
8
Min
15
15
15
40.0
Typ
Max
100
133
133
Unit
MHz
MHz
MHz
%
15pF load, -2, -3, -4 devices
Measured at 1.4V, F
OUT
= <66.66MHz 30pF load
50.0
60.0
Measured at 1.4V, F
OUT
= <50MHz 15pF load
Measured between 0.8V and 2.0V 30pF load
Measured between 0.8V and 2.0V 15pF load
Measured between 0.8V and 2.0V 30pF load
Measured between 2.0V and 0.8V 30pF load
Measured between 0.8V and 2.0V 15pF load
Measured between 2.0V and 0.8V 30pF load
All outputs equally loaded
45.0
50.0
55.0
2.50
1.50
1.50
2.50
1.50
1.25
200
%
nS
nS
nS
nS
nS
nS
( -2, -3, -4)
Output Rise Time ( -5H)
Output Fall Time ( -2, -3, -4)
Output Fall Time ( -2, -3, -4)
Output Fall Time
11
11
11
11
( -5H)
Output-to-output skew on
11
same bank ( -2, -3, -4)
Output-to-output skew
( -5H)
Output bank A -to- output
bank B skew ( -4, -5H)
Output bank A -to- output
bank B skew (-2, -3)
t
6
t
7
Delay, REF Rising Edge
11
to FBK Rising Edge
Device-to-Device Skew
11
All outputs equally loaded
200
pS
t
5
All outputs equally loaded
200
All outputs equally loaded
400
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of the device
Measured at 66.67MHz, loaded outputs, 15 pF load
0
0
±250
700
200
200
100
400
400
1.0
pS
pS
t
J
Cycle-to-cycle jitter
( -4, -5H)
11
Measured at 66.67MHz, loaded outputs, 30 pF load
Measured at 133MHz, loaded outputs, 15 pF load
pS
t
J
Cycle-to-cycle jitter (-2, -3)
11
Measured at 66.67MHz, loaded outputs, 30pF load
Measured at 66.67MHz, loaded outputs, 15pF load
pS
t
LOCK
PLL Lock Time
11
Stable power supply, valid clock presented on REF
and FBK pins
mS
Note: 11. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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