November 2006
rev 1.3
Pin Configuration
CLKIN
MRA
SR1
VSS
1
2
8
7
P2040A
VDD
SR0
ModOUT
SSON#
P2040A
3
4
6
5
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin
Name
CLKIN
MRA
SR1
VSS
SSON#
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull-up resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum
function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Power supply for the entire chip (3.3V)
Modulation Selection (Commercial)
MRA
0
0
0
0
1
1
1
1
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range
± 1.125
± 1.75
± 0.75
± 1.25
± 1.25
± 2.00
Reserved
Reserved
Modulation Rate (KHz)
(FIN /40) * 34.72KHz
(FIN /40) * 34.72KHz
(FIN /40) * 34.72KHz
(FIN /40) * 34.72KHz
(FIN /40) * 20.83KHz
(FIN /40) * 20.83KHz
Reserved
Reserved
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
