November 2006
rev 1.3
Pin Configuration
XIN /CLK
XOUT
DIV2
VSS
1
2
8
7
6
5
P2005A/S
VDD
ModOUT
SSON#
SR0
P2005A/S
3
4
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin
Name
XIN/CLK
XOUT
DIV2
VSS
SR0
SSON#
ModOUT
VDD
Type
I
O
I
P
I
I
O
P
Connect to crystal or clock.
Crystal output.
Description
Digital logic input used to select normal output mode or divide-by-two output mode. When
this pin is HIGH, the frequency of the output clock is the same as the input clock
frequency. When it is tied low, the output frequency is half the input clock frequency. This
pin has an internal pull-up resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to select Spreading Range
Refer Modulation Output and Spreading
Range Selection Table.
This pin has an internal pull-up resistor.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull-
low resistor.
Spread spectrum clock output.
Power supply for the entire chip (+3.3V or 5.0V)
Output Frequency Selections
Input Frequency
DIV2
0 (1/2 X)
1 (1X)
8MHz
4MHz
8MHz
12MHz
6MHz
12MHz
16MHz
8MHz
16MHz
20MHz
10MHz
20MHz
24MHz
12MHz
24MHz
28MHz
14MHz
28MHz
32MHz
16MHz
32MHz
Output
Frequency
Frequency Deviation Selections as a Function of Input Frequency
P/N
SR0
0
1
0
1
Input Frequency Range
8MHz
± 3.0%
± 2.5%
± 1.8%
± 1.5%
12MHz
± 2.5%
± 2.0%
± 1.5%
± 1.2%
16MHz
± 2.0%
± 1.8%
± 1.2%
± 1.1%
20MHz
± 1.8%
± 1.5%
± 1.1%
± 0.9%
24MHz
± 1.5%
± 1.3%
± 0.9%
± 0.8%
28MHz
± 1.5%
± 1.3%
± 0.9%
± 0.8%
32MHz
± 1.3%
± 1.0%
± 0.8%
± 0.6%
Modulation Rate
(KHz)
P2005A
(X
IN
/20) * 62.5
P2005S
Low Frequency EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
