May 2008
rev 0.2
Pin Diagram
PCS1P2859A
127MHz
VDD
AGND
CLKIN/XIN
XOUT
REFOUT
48MHz
48MHz
1
2
3
4
5
6
7
8
16
15
14
SHUTDOWNB
48M_ENBLB
AVDD
NC
NC
GND
33MHz
127MHz
PCS1P2859A
13
12
11
10
9
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
127MHz
VDD
AGND
CLKIN / XIN
XOUT
REFOUT
48MHz
48MHz
127MHz
33MHz
GND
NC
NC
AVDD
48M_ENBLB
SHUTDOWNB
Pin Type
Output
Power
Power
Input
Output
Output
Output
Output
Output
Output
Power
127MHz Clock Output
Connect to +3.3V
Connect to ground
Pin Description
External reference Clock or Input Crystal connection.
Connection to crystal. If using an external reference clock, this pin must be
left unconnected
25MHz Reference Clock output
48MHz Clock Output
48MHz Clock Output
127MHz Clock Output
33MHz Clock Output
Connect to ground
No connection
No connection
Power
Input
Input
Connect to +3.3V
48MHz Output Enable bit. When this pin is made LOW, the 48MHz clocks
are enabled.Tri-states 48MHz clocks when this pin is HIGH
.
Output Enable bit. When this pin is made HIGH, all clocks are enabled.
Tri-states all clocks when this pin is LOW
.
Multi-Output Clock Synthesizer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
