September 2006
rev 0.5
Pin Configuration
28 Pin SOIC Package -- Top View
V
DD
SDRAM0
SDRAM1
V
SS
V
DD
SDRAM2
SDRAM3
V
SS
BUF_IN
SDRAM4
SDRAM5
SDRAM12
V
DDIICC
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
16pi TSSOP
13
14
16
15
28
27
26
25
24
23
PCS2I2313ANZ
V
DD
SDRAM11
SDRAM10
V
SS
V
DD
SDRAM9
SDRAM8
V
SS
V
DD
SDRAM7
SDRAM6
V
SS
V
SSIIC
SCLK
PCS2I2314ANZ
22
21
20
19
18
17
Pin Description
Pins
1, 5, 20, 24, 28
4, 8, 17, 21, 25
13
16
9
14
15
2, 3, 6, 7, 10, 11, 12, 18, 19,
22, 23, 26, 27
Name
V
DD
V
SS
V
DDIIC
V
SSIIC
BUF_IN
SDATA
SCLK
SDRAM [0-12]
Type
P
P
P
P
I
I/O
I
O
Ground
Description
3.3V Digital Voltage supply
3.3V Serial Interface voltage supply
Ground for serial interface
Input clock .5V Tolerant
Serial data input, internal pull-up to V
DD
.5V Tolerant
Serial clock input, internal pull-up to V
DD
.5V Tolerant
SDRAM Clock Outputs
13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
