September 2006
rev 0.5
Serial Configuration Map
•
The Serial bits will be read by the clock driver in the
following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
•
Reserved bits should be programmed to “0” or ”1”.
•
Serial interface address for the PCS2I2313ANZ is:
PCS2I2313ANZ
Byte 1: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Pin #
27
26
23
22
--
--
19
18
Description
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
Reserved
Reserved
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Bit 2
Bit 1
Bit 0
Byte 0: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 2: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
11
10
--
--
7
6
3
2
Description
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Reserved
Reserved
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Pin #
--
12
--
--
--
--
--
--
Reserved
Description
SDRAM12 (Active/Inactive)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value
of all the bits is high after chip is powered up.
IIC Byte Flow
Byte
1
2
3
4
5
6
Description
IIC Address
Command (dummy value, ignored)
Byte Count (dummy value, ignored)
IIC Data Byte 0
IIC Data Byte 1
IIC Data Byte 2
13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
3 of 13
PULSECORE [ PulseCore Semiconductor ]
