September 2006
rev 0.3
Pin Description
Pin #
9,12
10,11
2,3,4,6,7
19,18,17,15,14
1
20
5
16
8
13
PCS2P3805E
Pin Names
OE
A
, OE
B
¯¯ ¯¯
IN
A
, IN
B
OA
1
-OA
5
OB
1
-OB
5
V
CCA
V
CCB
GND
A
GND
B
GND
Q
MON
Description
3-State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs from Bank A
Clock Outputs from Bank B
Power supply for Bank A
Power supply for Bank B
Ground for Bank A
Ground for Bank B
Ground
Monitor Output
Function Table
1
Inputs
OE
A
, OE
B
¯¯ ¯¯
L
L
H
H
Note: 1 H = HIGH; L = LOW; Z = High-Impedance
Outputs
IN
A
, IN
B
L
H
L
H
OA
n
, OB
n
L
H
Z
Z
MON
L
H
L
H
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
1
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
3
-
Max
4
6
Unit
pF
pF
Note: 1 This parameter is measured at characterization but not tested.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
