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PCS2I5T915AG 参数 Datasheet PDF下载

PCS2I5T915AG图片预览
型号: PCS2I5T915AG
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压( 2.5V )高精度1 : 5时钟扇出缓冲器 [Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 23 页 / 793 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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September 2006
rev 0.2
AC Electrical Characteristics Over Operating Range
5
Symbo
l
Skew Parameters
Single-Ended and Differential
Same Device Output
Modes
t
SK(O)
1
Pin-to-Pin Skew
Single-Ended in Differential
Mode (DSE)
Single-Ended and Differential
Modes
t
SK(INV)
Inverting Skew
2
Single-Ended in Differential
Mode (DSE)
Single-Ended and Differential
Modes
t
SK(P)
Pulse Skew
3
Single-Ended in Differential
Mode (DSE)
Single-Ended and Differential
Modes
t
SK(PP)
Part-to-Part Skew
4
Single-Ended in Differential
Mode (DSE)
HSTL and eHSTL Differential True and Complementary
V
OX
Output Crossing Voltage Level
Propagation Delay
Propagation Delay A to
2.5V / 1.8V LVTTL Outputs
t
PLH
Qn/Qn
t
PHL
HSTL / eHSTL Outputs
Output Rise Time
2.5V /1.8V LVTTL Outputs
t
R
(20% to 80%)
HSTL / eHSTL Outputs
Output Fall Time
2.5V /1.8V LVTTL Outputs
t
F
(20% to 80%)
HSTL / eHSTL Outputs
f
O
Frequency Range (HSTL/eHSTL outputs)
Frequency Range (2.5V/1.8V LVTTL outputs)
Output Gate Enable to Qn/Qn
Output Gate Enable to Qn/Qn Driven to GL Designated
Level
PCS2P5T915A
Parameter
Min
Typ
Max
Unit
25
pS
25
300
pS
300
300
pS
300
300
pS
300
V
DDQ
/2 - 200
V
DDQ
/2
V
DDQ
/2 + 200
2.5
2
350
350
350
350
1050
1350
1050
1350
250
200
3.5
3
mV
nS
pS
pS
MHz
Output Gate Enable/Disable Delay
t
PGE
t
PGD
nS
nS
Notes: 1. Skew measured between all outputs or output pairs under identical input and output interfaces, transitions and load conditions on any one device. For
single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through V
DDQ
/2. For differential LVTTL
outputs, the true outputs are compared only with other true outputs and the complementary outputs are compared only with other complementary
outputs. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals.
2. For operating with either 1.8V or 2.5V LVTTL output interfaces with both true and complementary outputs enabled. Inverting skew is the skew between
true and complementary outputs switching in opposite directions under identical input and output interfaces, transitions and load conditions on any one
device.
3. Skew measured is the difference between propagation delay times t
PHL
and t
PLH
of any output or output pair under identical input and output interfaces,
transitions and load conditions on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output
voltage passes through V
DDQ
/2. The measurement applies to both true and complementary signals. For differential HSTL outputs, the measurement
takes place at the crossing point of the true and complementary signals.
4. Skew measured is the magnitude of the difference in propagation times between any outputs or output pairs of two devices, given identical transitions
and load conditions at identical V
DD
/V
DDQ
levels and temperature.
5. Guaranteed by design.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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