September 2006
rev 1.1
Pulse
Generator
Z=50
Ω
Z
0
=50
Ω
PCS2I9940L
Z
0
=50
Ω
PCS2I9940L
R
T
=50
Ω
R
T
=50
Ω
V
TT
V
TT
Figure 1. LVCMOS_CLK PCS2I9940L AC Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
Differential
Pulse Generator
Z=50
Ω
Z
0
=50
Ω
PCS2I9940L
Z
0
=50
Ω
R
T
= 50
Ω
R
T
=50
Ω
V
TT
V
TT
Figure 2. PECL_CLK PCS2I9940L AC Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
PECL_CLK
PECL_CLK
V
PP
V
CMR
LVCMOS_CLK
V
C
V
CC
÷2
GND
V
CC
V
CC
÷2
Q
t
PD
GND
Q
t
PD
V
C
V
CC
÷2
GND
Figure 3. Propagation Delay (t
PD
) Test Reference
V
CC
V
CC
÷2
GND
t
P
Figure 4. LVCMOS Propagation Delay (t
PD
) Test Reference
V
CC
V
CC
÷2
GND
V
OH
T
0
DC (t
P
÷T
0
Χ
100%)
t
SK(O)
V
CC
÷2
GND
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 5. Output Duty Cycle (DC)
V
CC
= 3.3V V
CC
= 2.5V
2.4
0.55
t
F
t
R
1.8V
0.6V
t
F
Figure 6. Output–to–Output Skew t
SK(O)
V
CC
= 3.3V V
CC
= 2.5V
2.0
0.8
t
R
1.7V
0.7V
Figure 7. Output Transition Time Test Reference
Figure 8. Input Transition Time Test Reference
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
7 of 13
PULSECORE [ PulseCore Semiconductor ]
