欢迎访问ic37.com |
会员登录 免费注册
发布采购

PCS2I9940LG-32-LT 参数 Datasheet PDF下载

PCS2I9940LG-32-LT图片预览
型号: PCS2I9940LG-32-LT
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压1:18时钟分配芯片 [Low Voltage 1:18 Clock Distribution Chip]
分类和应用: 时钟
文件页数/大小: 13 页 / 485 K
品牌: PULSECORE [ PulseCore Semiconductor ]
 浏览型号PCS2I9940LG-32-LT的Datasheet PDF文件第4页浏览型号PCS2I9940LG-32-LT的Datasheet PDF文件第5页浏览型号PCS2I9940LG-32-LT的Datasheet PDF文件第6页浏览型号PCS2I9940LG-32-LT的Datasheet PDF文件第7页浏览型号PCS2I9940LG-32-LT的Datasheet PDF文件第9页浏览型号PCS2I9940LG-32-LT的Datasheet PDF文件第10页浏览型号PCS2I9940LG-32-LT的Datasheet PDF文件第11页浏览型号PCS2I9940LG-32-LT的Datasheet PDF文件第12页  
September 2006
rev 1.1
Power Consumption of the PCS2I9940L and
Thermal Management
The PCS2I9940L AC specification is guaranteed for the
entire operating frequency range up to 250MHz. The
PCS2I9940L power consumption and the associated
long-term reliability may decrease the maximum
frequency limit, depending on operating conditions such
as clock frequency, supply voltage, output loading,
ambient temperature, vertical convection and thermal
conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the
PCS2I9940L die junction temperature and the associated
device reliability.
PCS2I9940L
Where I
CCQ
is the static current consumption of the
PCS2I9940L, C
PD
is the power dissipation capacitance
per output, (M)∑C
L
represents the external capacitive
output load, N is the number of active outputs (N is
always 12 in case of the PCS2I9940L). The PCS2I9940L
supports driving transmission lines to maintain high signal
integrity and tight timing parameters. Any transmission
line will hide the lumped capacitive load at the end of the
board trace, therefore,
∑C
L
is zero for controlled
transmission line systems and can be eliminated from
equation 1. Using parallel termination output termination
results in equation 2 for power dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, V
OL
, I
OL
, V
OH
and I
OH
are
a function of the output termination technique and DC
Q
is
the clock signal duty cycle. If transmission lines are used
∑C
L
is zero in equation 2 and can be eliminated. In
general, the use of controlled transmission line
techniques eliminates the impact of the lumped capacitive
loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die
junction temperature T
J
as a function of the power
consumption.
Where R
thja
is the thermal impedance of the package
(junction to ambient) and T
A
is the ambient temperature.
According to Table 11, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the PCS2I9940L in a
series terminated transmission line system, equation 4.
Table 11. Die junction temperature and MTBF
Junction temperature
(°C)
100
110
MTBF (Years)
20.4
9.1
120
4.2
130
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the PCS2I9940L
needs to be controlled and the thermal impedance of the
board/package should be optimized. The power
dissipated in the PCS2I9940L is represented in
equation 1.

P
TOT
= 
I
CCQ
+
V
CC
f
CLOCK
⋅ 
N
C
PD
+
C
L
 ⋅
V
CC
M


P
TOT
=
V
CC
⋅ 
I
CCQ
+
V
CC
f
CLOCK
⋅ 
N
C
PD
+
C
L
 +
DC
Q
I
OH
(
V
CC
V
OH
)
+
(
1
DC
Q
)
I
OL
V
OL
M

P
T
J
=
T
A
+
P
TOT
R
thja
Equation
1
[
]
Equation
2
Equation
3
Equation
4
f
CLOCKMAX
=
C
PD
1
2
N
V
CC
T
T
A
⋅ 
JMAX
(
I
CCQ
V
CC
)
R
thja
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
8 of 13