September 2006
rev 0.3
Test Circuits and Waveforms
V
CC
6V
GND
500Ω
V
IN
Pulse
Generator
R
T
D.U.T
50pF
500Ω
V
OUT
PCS2P3805A
Switch Position
Test
Disable Low
Enable Low
Disable High
Enable High
Definitions:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to
Z
OUT
of the Pulse
Generator.
Switch
6V
GND
Test Circuits for All Outputs
3V
INPUT
t
PLH
OUTPUT
t
R
t
F
t
PHL
2.0V
0.8V
1.5V
0V
V
OH
1.5V
V
OL
INPUT
t
PLH1
OUTPUT 1
t
SK(O)
OUTPUT 2
t
SK(O)
t
PHL1
3V
V
OH
1.5V
V
OL
V
OH
Package Delay
3V
INPUT
t
PLH
OUTPUT
t
SK(P)
= | t
PLH
- t
PLH
|
t
PHL
1.5V
0V
V
OH
1.5V
V
OL
t
PLH2
t
PHL2
t
SK(O)
= | t
PLH2
- t
PLH1
| or | t
PHL2
- t
PHL1
|
Output Skew – t
SK(o)
INPUT
t
PLH1
Package 1
OUTPUT
t
SK(t)
Package 2
OUTPUT
t
PLH2
t
PHL2
t
SK(t)
t
PHL1
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
Pulse Skew
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t
PZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
3.5V
1.5V
t
PHZ
0.3V
V
OH
0V
t
PLZ
0.3V
DISABLE
3V
1.5V
0V
3.5V
V
OL
t
SK(t)
= | t
PLH2
- t
PLH1
| or | t
PHL2
- t
PHL1
|
Package Skew – t
SK(t)
Note:
Pulse Generator for all Pulses:f
≤
10MHz; t
F
≤
2.5nS; t
R
≤
2.5nS
Enable and Disable Times
Note:
Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
3.3V CMOS Buffer Clock Driver
Notice: The information in this document is subject to change without notice.
7 of 12
PULSECORE [ PulseCore Semiconductor ]
