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PCS2P3805AG-20-AT 参数 Datasheet PDF下载

PCS2P3805AG-20-AT图片预览
型号: PCS2P3805AG-20-AT
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V CMOS缓冲器时钟驱动器 [3.3V CMOS Buffer Clock Driver]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 12 页 / 232 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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September 2006
rev 0.3
Switching Characteristics Over Operating Range – Commercial
3,4
Symbol
t
PLH
t
PHL
t
R
t
F
t
SK(O)
t
SK(P)
PCS2P3805A
Parameter
Propagation Delay
IN
A
to OA
n
, IN
B
to OB
n
Output Rise Time (0.8V to 2.0V)
Output Fall Time (2.0V to 0.8V)
Output skew: skew between outputs of all
banks of same package
(inputs tied together)
Pulse skew: skew between opposite
transitions of same output (|t
PHL
-– t
PLH
|)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Output Enable Time
OE
A
to OA
n
, OE
B
to OB
n
¯¯
¯¯
Output Disable Time
OE
A
to OA
n
, OE
B
to OB
n
¯¯
¯¯
Conditions
1
PCS2P3805A
Min
1.5
2
Max
5
2
2
0.5
Unit
nS
nS
nS
nS
nS
C
L
= 50pF
R
L
= 500Ω
1
t
SK(T)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.2
nS
1.5
1.5
6
5
nS
nS
Switching Characteristics Over Operating Range – Industrial
3,4
Symbol
t
PLH
t
PHL
t
R
t
F
t
SK(O)
t
SK(P)
Parameter
Propagation Delay
IN
A
to OA
n
, IN
B
to OB
n
Output Rise Time
(0.8V to 2.0V)
Output Fall Time
(2.0V to 0.8V)
Output skew: skew between outputs of all
banks of same package (inputs tied
together)
Pulse skew: skew between opposite
transitions of same output (|t
PHL
-– t
PLH
|)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
Output Enable Time
OE
A
to OA
n
,
OE
B
to OB
n
¯¯
¯¯
Output Disable Time
OE
A
to OA
n
,
OE
B
to OB
n
¯¯
¯¯
Conditions
1
PCS2P3805A
Min
1.5
2
Max
5.2
2
2
0.6
Unit
nS
nS
nS
nS
nS
C
L
= 50pF
R
L
= 500Ω
1
t
SK(T)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.2
nS
1.5
1.5
6
5
nS
nS
Note: 1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH
, t
PHL
, t
SK(t)
are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
CC
, operating temperature and process parameters. These propagation delay
limits do not imply skew.
3.3V CMOS Buffer Clock Driver
Notice: The information in this document is subject to change without notice.
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