September 2006
rev 0.2
DC Electrical Characteristics Over Operating Range for 1.8V LVTTL
1
Symbol
I
IH
I
IL
V
IK
V
IN
V
IH
V
IL
V
DIF
V
CM
V
IH
V
IL
V
REF
PCS2P5T915A
Parameter
Test Conditions
V
DD
= 2.6V
V
DD
= 2.6V
V
I
= V
DDQ
/GND
V
I
= GND/V
DDQ
-0.7
- 0.3
1.073
11
0.683
11
0.2
825
V
REF
+ 100
V
REF
- 100
900
900
975
Min
Typ
8
Max
±5
±5
- 1.2
V
DDQ
+ 0.3
Unit
Input Characteristics
Input HIGH Current
12
Input LOW Current
12
Clamp Diode Voltage
DC Input Voltage
2
µA
V
V
V
V
V
mV
mV
mV
mV
V
DD
= 2.4V, I
IN
= -18mA
Single-Ended Inputs
DC Input HIGH
DC Input LOW
DC Differential Voltage
3,9
DC Common Mode Input
Voltage
4,9
DC Input HIGH
5,6,9
DC Input LOW
Single-Ended Reference
5,9
Voltage
I
OH
= -6mA
I
OH
= -100µA
I
OL
= 6mA
I
OL
= 100µA
5,7,9
Differential Inputs
Output Characteristics
V
OH
V
OL
Output HIGH Voltage
Output LOW Voltage
V
DDQ
- 0.4
V
DDQ
- 0.1
0.4
0.1
V
V
V
V
Notes:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to V
DD
/2 and A/V
REF
is tied to GND.
3. V
DIF
specifies the minimum input differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement"
input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC
differential voltage must be achieved to guarantee switching to a new state.
4. V
CM
specifies the maximum allowable range of (V
TR
+ V
CP
) /2. Differential mode only.
5. For single-ended operation in differential mode, A/V
REF
is tied to the DC voltage V
REF
. The input is guaranteed to toggle within ±200mV of V
REF
when
V
REF
is constrained within +600mV and V
DDI
-600mV, where V
DDI
is the nominal 1.8V power supply of the device driving the A input. To guarantee
switching in voltage range specified in the JEDEC 1.8V LVTTL interface specification, V
REF
must be maintained at 900mV with appropriate
tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at V
DD
= 2.5V, V
DDQ
= 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The
correct input interface table should be referenced.
10. This value is the worst case minimum V
IH
over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is V
IH
= 0.65 • V
DD
where V
DD
is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the
specification, the translator was designed to accept the calculated worst case value ( V
IH
= 0.65 • [1.8 - 0.15V]) rather than reference against a
nominal 1.8V supply.
11. This value is the worst case maximum V
IL
over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is V
IL
= 0.35 • V
DD
where V
DD
is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure
compliance with the specification, the translator was designed to accept the calculated worst case value ( V
IL
= 0.35 • [1.8 + 0.15V])
rather than reference against a nominal 1.8V supply.
12. For differential mode (RxS = LOW), A and A/V
REF
must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
