September 2006
rev 0.2
PCS2P5T915A
AC Differential Input Specifications1
Symbol
Parameter
Min
1.73
Typ
Max
Unit
Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)2
t W
nS
Reference Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL
2.17
outputs)2
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF
AC Differential Voltage3
AC Input HIGH4,5
AC Input LOW4,6
400
mV
mV
mV
VIH
Vx + 200
VIL
Vx - 200
LVEPECL
VDIF
AC Differential Voltage3
AC Input HIGH4
AC Input LOW4
400
mV
mV
mV
VIH
VIL
1275
875
Notes: 1. For differential input mode, RxS is tied to GND.
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and
the voltage range defined by VDIF has been met or exceeded.
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the
"complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state.
4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range.
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
14 of 23
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
