May 2008
rev 0.1
Pin Configuration for PCS3P624Z09B/C
PCS3P624Z05B/C
PCS3P624Z09B/C
CLKIN
1
CLKOUTA1
2
CLKOUTA2
3
VDD
4
GND
PCS3P624Z09B/C
5
16
15
14
13
12
11
10
9
DLY_CTRL
CLKOUTA4
CLKOUTA3
VDD
GND
CLKOUTB4
CLKOUTB3
S1
CLKOUTB1
6
CLKOUTB2
7
S2
8
Pin Description for PCS3P624Z09B/C
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
1
CLKOUTA1
2
CLKOUTA2
2
VDD
GND
CLKOUTB1
S2
3
S1
3
CLKOUTB3
2
CLKOUTB4
2
GND
VDD
CLKOUTA3
2
CLKOUTA4
2
DLY_CTRL
2
2
Pin Type
I
O
O
P
P
O
O
I
I
O
O
P
P
O
O
O
Buffered clock Bank A output
4
Buffered clock Bank A output
4
3.3V supply
Ground
Buffered clock Bank B output
4
Buffered clock Bank B output
4
Description
External reference Clock input, 5V tolerant input
CLKOUTB2
2
Select input, bit 2.See
Select Input Decoding table for PCS3P624Z09
for more details
Select input, bit 1.See
Select Input Decoding table for PCS3P624Z09
for more details
Buffered clock Bank B output
4
Buffered clock Bank B output
4
Ground
3.3V supply
Buffered clock Bank A output
4
Buffered clock Bank A output
4
External Input-Output Delay control
. This pin can be used as clock output
Notes: 1. Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
High Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
