P4C422
FUNCTIONAL DESCRIPTION
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When the chip select
one(CS1)andthewriteenable(WE)areLOWandthechip
select two (CS2) is HIGH, the information on data inputs
(D0 throughD3)iswrittenintotheaddressedmemoryword
and preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
recovery times by eliminating the “write recovery glitch.”
Readingisperformedwithchipselctone (CS1)LOW, chip
select two (CS2) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O0 through O3). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS1) is HIGH, or during the write operation when write
enable (WE) is LOW.
TRUTH TABLE
Notes:
Mode
CS2 CS1 WE OE
Output
High Z
High Z
High Z
DOUT
H
L
X
= HIGH
= Low
= Don't Care
Standby
Standby
DOUT Disabled
Read
L
X
H
H
H
X
H
L
X
X
X
H
L
X
X
H
L
HIGH Z = Implies outputs are disabled or off. This condition
is defined as high impedance state for the
P4C422.
L
Write
L
X
High Z
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10% except as noted, All Temperature Ranges)(2)
-12
-25
-20
-10*
-15
-35
Max
Parameter
Read Cycle Time (5)
Sym.
tRC
Unit
Max
Max Min Max
Min
Min Max Min Max Min
Min
35
12
12
15
20
25
ns
tACS
Chip Select Time (5)
8
15
12
7.5
8
25 ns
30 ns
Chip Select to High-Z (6)
Output Enable Time
tZRCS
tAOS
tZROS
tAA
8
7.5
8
10
8
12
8
15
12
15
20
20
15
20
25
25
30
ns
ns
Output Enable to High-Z(6)
Address Access Time (5)
10
12
12
15
10
35
ns
*VCC = 5V ± 5%
TIMING WAVEFORM OF READ CYCLE
Document # SRAM101 REV. A
Page 3 of 10
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