Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
2
2.1
Configuration
Chip Configuration for PG-TFBGA-68
This chapter contains the chip configuration and addressing.
The chip configuration of a DDR2 SDRAM is listed by function in
The abbreviations used in the Ball# and Buffer Type
columns are explained in
and
respectively. The ball numbering for the FBGA package is depicted in figures.
TABLE 7
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball
Type
I
I
I
I
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2
Note: 1 Gbit components and higher
Chip Select
Bank Address Bus 1:0
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Function
Clock Signals
×4×8
Organizations
J8
K8
K2
K7
L7
K3
L8
L2
L3
L1
CK
CK
CKE
RAS
CAS
WE
CS
BA0
BA1
BA2
Clock Signal CK, CK
Control Signals
×4×8
Organizations
Address Signals
×4×8
Organizations
Rev. 1.3, 2007-07
03062006-ZNH8-HURV
9
QIMONDA [ QIMONDA AG ]
