Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
2
2.1
Pin Configuration
Pin Configuration
and
respectively. The pin numbering is depicted in
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in
(240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in
TABLE 5
Pin Configuration of RDIMM
Pin No.
Clock Signals
185
186
52
171
CK0
CK0
CKE0
CKE1
NC
Control Signals
193
76
220
221
192
74
73
18
Address Signals
71
190
54
BA0
BA1
BA2
NC
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Bank Address Bus 1:0
S0
S1
S2
S3
RAS
CAS
WE
RESET
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
CMOS
Register Reset
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select Rank 3:0
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
—
Clock Enables 1:0
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Clock Signal CK0, Complementary Clock Signal CK0
Name
Pin
Type
Buffer
Type
Function
Rev. 1.0, 2006-12
11032006-VX0M-M6IH
5
QIMONDA [ QIMONDA AG ]
