Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
Ball#
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
Ball
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
—
I
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Address Signal 12:0, Address Signal 10/Autoprecharge
Address Signal 13
Note: x4/x8 512 Mbit components
Note: x16 512 Mbit components
Bank Address Bus 1:0
Address Signals
×16
organization
L2
L3
L1
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
C8
C2
D7
D3
BA0
BA1
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
DQ0
DQ1
DQ2
DQ3
Address Signal 12:0, Address Signal 10/Autoprecharge
Data Signals
×4/×8
organization
Data Signal 3:0
Rev. 1.12, 2007-05
10062006-YPTZ-CDR7
11
QIMONDA [ QIMONDA AG ]
