Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
2
2.1
Configuration
Chip Configuration
This chapter contains the Chip Configuration.
The chip configuration of a DDR2 SDRAM is listed by function in
The abbreviations used in the Ball# and Buffer Type
columns are explained in
and
respectively. The ball numbering for the FBGA package is depicted in
for
×4,
for
×8
and
for
×16.
TABLE 7
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball
Type
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Enable
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Enable
Note: See functional description in x4/x8 organization
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 1:0
Function
Clock Signals
×4/×8
organization
E8
F8
F2
J8
K8
K2
CK
CK
CKE
CK
CK
CKE
Clock Signal CK, Complementary Clock Signal CK
Clock Signals
×16
organization
Control Signals
×4/×8
organizations
F7
G7
F3
G8
K7
L7
K3
L8
G2
G3
RAS
CAS
WE
CS
RAS
CAS
WE
CS
BA0
BA1
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Control Signals
×16
organization
Address Signals
×4/×8
organizations
Rev. 1.12, 2007-05
10062006-YPTZ-CDR7
10
QIMONDA [ QIMONDA AG ]
