Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
2.3
256-Mbit DDR2 Addressing
TABLE 12
DDR2 Addressing for
×8
Organization
This chapter describes the 256-Mbit DDR2 addressing.
Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
Page Size [Bytes]
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2
colbits
×
org/8 [Bytes]
32Mb x 8
1)
BA[1:0]
4
A10 / AP
A[12:0]
A[9:0]
10
8
1024 (1K)
Note
2)
3)
TABLE 13
DDR2 Addressing for
×16
Organization
Configuration
Bank Address
Number of Banks
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
Page Size [Bytes]
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2
colbits
×
org/8 [Bytes]
16Mb x 16
1)
BA[1:0]
4
A10 / AP
A[12:0]
A[8:0]
9
16
1024 (1K)
Note
2)
3)
Rev. 1.3, 2007-05
07182006-DD60-22E6
14
QIMONDA [ QIMONDA AG ]
