Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
3
Functional Description
This chapter contains the functional description.
TABLE 14
Mode Register Definition (BA[2:0] = 000B)
Field
BA2
Bits
16
Type
1)
reg. addr.
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0
B
BA1
BA0
A13
15
14
13
BA2
Bank Address
Bank Address [1]
BA1
Bank Address
0
B
Bank Address [0]
0
B
BA0
Bank Address
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0
B
PD
12
w
A13
Address bit 13
Active Power-Down Mode Select
0
B
PD
Fast exit
1
B
PD
Slow exit
Write Recovery
2)
Note: All other bit combinations are illegal.
001
B
010
B
011
B
100
B
101
B
DLL
8
w
WR
2
WR
3
WR
4
WR
5
WR
6
WR
[11:9]
w
DLL Reset
0
B
DLL
No
1
B
DLL
Yes
Test Mode
0
B
TM
Normal Mode
1
B
TM
Vendor specific test mode
TM
7
w
Rev. 1.3, 2007-05
07182006-DD60-22E6
15
QIMONDA [ QIMONDA AG ]
