Internet Data Sheet
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
240-Pin Registered DDR2 SDRAM
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–F0”, where 4200P
means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe
(CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2
and produced on the Raw Card “F”
TABLE 3
Address Format Table
DIMM
Density
512 MB
1 GB
1 GB
2 GB
2 GB
Module
Organization
64M
×72
128M
×72
128M
×72
256M
×72
256M
×72
Memory
Ranks
1
1
2
2
2
ECC/
Non-ECC
ECC
ECC
ECC
ECC
ECC
# of SDRAMs # of row/bank/column
bits
9
18
18
36
36
14/2/10
14/2/11
14/2/10
14/2/11
14/2/11
Raw
Card
F
H
G
J
L
TABLE 4
Components on Modules
Product Type
1)
HYS72T64000HP
HYS72T128000HP
HYS72T128020HP
HYS72T256220HP
DRAM Components
HYB18T512800BF
HYB18T512400BF
HYB18T512800BF
HYB18T512400BF
DRAM Density
512 Mbit
512 Mbit
512 Mbit
512 Mbit
DRAM Organisation
512M × 8
512M × 4
512M × 8
512M × 4
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
5
QIMONDA [ QIMONDA AG ]
