HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 6
Ball#/Pin#
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
Pin Configuration of DDR2 SDRAM
Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
–
I
I
–
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
SSTL
SSTL
–
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
8
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
Data Signal 3:0
Address Signal 12:0, Address Signal 10/Autoprecharge
Address Signal 13
Note: x4/x8 512 Mbit components
Note: and x16 512 Mbit components
Bank Address Bus 1:0
Function
Address Signal 12:0, Address Signal 10/Autoprecharge
Address Signals
×16
organization
L2
L3
L1
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
C8
C2
D7
D3
BA0
BA1
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
DQ0
DQ1
DQ2
DQ3
Data Signals
×4
organizations
Internet Data Sheet
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