HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
2
2.1
Pin Configuration
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in
The abbreviations used in the Pin# and
Buffer Type columns are explained in
and
respectively. The pin numbering for the FBGA package
is depicted in Figure 1 for
×4,
Figure 2 for
×8
and Figure 3 for
×16.
Table 6
Ball#/Pin#
Pin Configuration of DDR2 SDRAM
Name
Pin
Type
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Enable
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Enable
Note: See functional description in x4/x8 organization
Control Signals
×4/×8
organizations
F7
G7
F3
G8
K7
L7
K3
L8
G2
G3
RAS
CAS
WE
CS
RAS
CAS
WE
CS
BA0
BA1
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Chip Select
Bank Address Bus 1:0
Chip Select
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Function
Clock Signals
×4/×8
organizations
E8
F8
F2
J8
K8
K2
CK
CK
CKE
CK
CK
CKE
Clock Signal CK, Complementary Clock Signal CK
Clock Signals
×16
organization
Control Signals
×16
organization
Address Signals
×4/×8
organizations
Internet Data Sheet
7
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
