Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
2
Chip Configuration
The chip configuration of a DDR SGRAM is listed by function in
The abbreviations used in the Pin#/Buffer# column
are explained in
and
respectively. The chip numbering for TSOP is depicted in
TABLE 3
Chip Configuration
Ball#
Clock Signals
45
46
44
Control Signals
23
22
21
24
26
27
29
30
31
32
35
36
37
38
39
40
28
41
42
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
NC
17
A13
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
I
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
—
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Note: Module based on 128 Mbit or smaller dies
Address Signal 13
Note: 1 Gbit based module
Note: Module based on 512 Mbit or smaller dies
Address Bus 11:0
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Bank Address Bus 2:0
CK
CK
CKE
I
I
I
SSTL
SSTL
SSTL
Clock Signal
Complementary Clock Signal
Clock Enable
Name
Pin
Type
Buffer
Type
Function
Address Signals
Rev. 1.1, 2007-01
03292006-SR4U-HULB
5
QIMONDA [ QIMONDA AG ]
