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HYI18T1G400BC-3 参数 Datasheet PDF下载

HYI18T1G400BC-3图片预览
型号: HYI18T1G400BC-3
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位双数据速率- SDRAM双 [1-Gbit Double-Data-Rate-Two SDRAM]
分类和应用: 动态存储器
文件页数/大小: 74 页 / 4044 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)  
1-Gbit Double-Data-Rate-Two SDRAM  
1
Overview  
This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main  
characteristics.  
1.1  
Features  
The 1-Gbit Double-data-Rate SDRAM offers the following key features:  
1.8 V ± 0.1 V Power Supply  
Off-Chip-Driver impedance adjustment (OCD) and On-  
Die-Termination (ODT) for better signal quality  
Auto-Precharge operation for read and write bursts  
Auto-Refresh, Self-Refresh and power saving Power-  
Down modes  
Average Refresh Period 7.8 µs at a TCASE lower than  
85 °C, 3.9 µs between 85 °C and 95 °C  
Programmable self refresh rate via EMRS2 setting  
Programmable partial array refresh via EMRS2 settings  
DCC enabling via EMRS2 setting  
1.8 V ± 0.1 V (SSTL_18) compatible I/O  
DRAM organizations with 4, 8 and 16 data in/outputs  
Double Data Rate architecture: two data transfers per  
clock cycle four internal banks for concurrent operation  
Programmable CAS Latency: 3, 4, 5 and 6  
Programmable Burst Length: 4 and 8  
Differential clock inputs (CK and CK)  
Bi-directional, differential data strobes (DQS and DQS) are  
transmitted / received with data. Edge aligned with read  
data and center-aligned with write data  
DLL aligns DQ and DQS transitions with clock  
DQS can be disabled for single-ended data strobe  
operation  
Commands entered on each positive clock edge, data and  
data mask are referenced to both edges of DQS  
Data masks (DM) for write data  
Posted CAS by programmable additive latency for better  
command and data bus efficiency  
Full and reduced Strength Data-Output Drivers  
1K page size for ×4 & ×8, 2K page size for ×16  
Package: P(G)-TFBGA-68 , P(G)-TFBGA-84  
and PG-TFBGA-92  
RoHS Compliant Products1)  
All Speed grades faster than DDR2–400 comply with  
DDR2–400 timing specifications when run at a clock rate  
of 200 MHz.  
TABLE 1  
Performance Tables for –2.5(F)  
Product Type Speed Code  
Speed Grade  
–2.5F  
–2.5  
Unit  
DDR2–800D 5–5–5  
DDR2–800E 6–6–6  
Max. Clock Frequency  
@CL6 fCK6 400  
@CL5 fCK5 400  
400  
333  
266  
200  
15  
MHz  
MHz  
MHz  
MHz  
ns  
@CL4 fCK4 266  
@CL3 fCK3 200  
tRCD 12.5  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
tRP 12.5  
15  
ns  
tRAS 45  
45  
ns  
tRC 57.5  
60  
ns  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 1.3, 2007-07  
3
03062006-ZNH8-HURV