Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
3
Functional Description
TABLE 4
Truth Table: Operation Command
This chapter lists all defined commands and their usage for this Synchronous DRAM.
Operation
Bank Active
Bank Precharge
Precharge All
Write
Write with Auto
precharge
Read
Read with Auto
precharge
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Clock Suspend Entry
Power Down Entry
(Precharge or active
standby)
Clock Suspend Exit
Power Down Exit
Data Write/Output
Enable
Data Write/Output
Disable
1)
2)
3)
4)
Device State
Idle
3)
Any
Any
Active
Active
Active
Active
Idle
Any
Active
Any
Idle
Idle
Idle
(Self Refr.)
Active
Idle
Active
Active
4)
CKE
n-1
1)2)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
CKE
n
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
DQM
BA0
BA1
V
V
X
V
V
V
V
V
X
X
X
X
X
X
X
X
AP=
A10
V
L
H
L
H
L
H
V
X
X
X
X
X
X
X
X
Addr. CS
RAS
CAS
WE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
X
X
X
H
X
X
L
X
X
L
L
H
H
H
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
Any
(Power Down)
Active
Active
V = Valid, x = Don’t Care, L = Low Level, H = High Level
CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.
This is the state of the banks designated by BA0, BA1 signals.
Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in clock suspend
mode.
Rev. 1.1, 2007-02
09072006-N4GC-EREN
8
QIMONDA [ QIMONDA AG ]
