Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Ball No.
188
183
63
182
61
60
180
58
179
177
70
57
176
196
Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
I
NC
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
—
Function
Address Bus 12:0
Address Signal 13
Note: 1 Gbit based module and 512M
×4/×8
Not Connected
Note: Module based on 1 Gbit
×
16 Module based on 512 Mbit
×
16 or smaller
Address Signal 14
Note: Modules based on 2 Gbit
Not Connected
Note: Modules based on 1 Gbit or smaller
Data Bus 63:0
Data Input/Output pins
174
A14
NC
Data Signals
3
4
9
10
122
123
128
129
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
8
QIMONDA [ QIMONDA AG ]
