Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
3.3
Timing Characteristics
3.3.1
Speed Grade Definitions
TABLE 12
Speed Grade Definition
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Period
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Symbol
DDR2–800D
–25F
5–5–5
Min.
5
3.75
2.5
2.5
45
57.5
12.5
12.5
Max.
8
8
8
8
70k
—
—
—
DDR2–800E
–2.5
6–6–6
Min.
5
3.75
3
2.5
45
60
15
15
Max.
8
8
8
8
70k
—
—
—
Unit
Note
t
CK
—
ns
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
TABLE 13
Speed Grade Definition
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Period
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Symbol
DDR2–667C
–3
4–4–4
Min.
5
3
3
45
57
12
12
Max.
8
8
8
70k
—
—
—
DDR2–667D
–3S
5–5–5
Min.
5
3.75
3
45
60
15
15
Max.
8
8
8
70k
—
—
—
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
Max.
8
8
8
70k
—
—
—
Unit
Note
t
CK
—
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) mentioned in Component datasheet.
Rev. 1.13, 2007-10
08212006-PKYN-2H1B
15
QIMONDA [ QIMONDA AG ]
