Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
2
2.1
Pin Configurations
Chip Configuration
The chip configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in
(200 balls). The abbreviations
used in columns Ball and Buffer Type are explained in
and
respectively. The Ball numbering is depicted in
TABLE 5
Chip Configuration of SO-DIMM
Ball No.
Clock Signals
30
164
32
166
79
80
CK0
CK1
CK0
CK1
CKE0
CKE1
NC
Control Signals
110
115
S0
S1
NC
108
113
109
Address Signals
107
106
85
BA0
BA1
BA2
NC
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Less than 1Gb DDR2 SDRAMS
Bank Address Bus 2:0
RAS
CAS
WE
I
I
NC
I
I
I
SSTL
SSTL
—
SSTL
SSTL
SSTL
Not Connected
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select Rank 1:0
I
I
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Clock Enable Rank 1:0
Note: 2 Ranks module
Not Connected
Note: 1-rank module
Clock Signals 2:0, Complement Clock Signals 2:0
Name
Pin
Type
Buffer
Type
Function
Rev. 1.1, 2007-01
08212006-PKYN-2H1B
6
QIMONDA [ QIMONDA AG ]
