Internet Data Sheet
HYS72D[64/128/256]xxxHBR–[5/6]–C
Registered Double-Data-Rate SDRAM Module
TABLE 9
I
DD
Conditions
Parameter
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE
≤
V
IL,MAX
Precharge Floating Standby Current
CS
≥
V
IH,,MIN
, all banks idle; CKE
≥
V
IH,MIN
;
address and other control inputs changing once per clock cycle;
V
IN
=
V
REF
for DQ, DQS and DM.
Precharge Quiet Standby Current
CS
≥
V
IHMIN
, all banks idle; CKE
≥
V
IH,MIN
;
V
IN
=
V
REF
for DQ, DQS and DM;
address and other control inputs stable at
≥
V
IH,MIN
or
≤
V
IL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE
≤
V
ILMAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Standby Current
one bank active; CS
≥
V
IH,MIN
; CKE
≥
V
IH,MIN
;
t
RC
=
t
RAS,MAX
;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B;
I
OUT
= 0 mA
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t
RC
=
t
RFCMIN
, burst refresh
Self-Refresh Current
CKE
≤
0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
Rev. 1.22, 2007-08
03292006-6N25-8R3I
12
QIMONDA [ QIMONDA AG ]
