HYS72D64300HU-6-B 参数 Datasheet PDF下载

Internet Data Sheet

HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

TABLE 2

Ordering Information

Type

PC3200 (CL=3.0)

HYS64D64300GU–5–B

HYS72D64300GU–5–B

HYS64D128320GU–5–B

HYS72D128320GU–5–B

PC2700 (CL=2.5)

HYS64D64300GU–6–B

HYS72D64300GU–6–B

HYS64D128320GU–6–B

HYS72D128320GU–6–B

PC3200 (CL=3.0)

HYS64D32301HU–5–B

HYS64D64300HU–5–B

HYS72D64300HU–5–B

HYS64D128320HU–5–B

HYS72D128320HU–5–B

PC2700 (CL=2.5)

HYS64D64300HU–6–B

HYS72D64300HU–6–B

HYS64D128320HU–6–B

HYS72D128320HU–6–B

PC2700U–25330–A0

PC2700U–25330–A0

PC2700U–25330–B0

PC2700U–25330–B0

one rank 512 MB DIMM

one rank 512 MB ECC-DIMM

two ranks 1 GB DIMM

two ranks 1 GB ECC-DIMM

512 Mbit (×8)

512 Mbit (×8)

512 Mbit (×8)

512 Mbit (×8)

PC3200U–30330–C0

PC3200U–30330–A0

PC3200U–30330–A0

PC3200U–30330–B0

PC3200U–30330–B0

one rank 256 MB DIMM

one rank 512 MB DIMM

one rank 512 MB ECC-DIMM

two ranks 1 GB DIMM

two ranks 1 GB ECC-DIMM

512 Mbit (×16)

512 Mbit (×8)

512 Mbit (×8)

512 Mbit (×8)

512 Mbit (×8)

PC2700U–25330–A0

PC2700U–25330–A0

PC2700U–25330–B0

PC2700U–25330–B0

one rank 512 MB DIMM

one rank 512 MB ECC-DIMM

two ranks 1 GB DIMM

two ranks 1 GB ECC-DIMM

512 Mbit (×8)

512 Mbit (×8)

512 Mbit (×8)

512 Mbit (×8)

PC3200U–30330–A0

PC3200U–30330–A0

PC3200U–30330–B0

PC3200U–30330–B0

one rank 512 MB DIMM

one rank 512 MB ECC-DIMM

two ranks 1 GB DIMM

two ranks 1 GB ECC-DIMM

512 Mbit (×8)

512 Mbit (×8)

512 Mbit (×8)

512 Mbit (×8)

Compliance Code

Description

SDRAM Technology

Note: All part numbers end with a place code designating the silicon-die revision. Reference information available on request.

Example: HYS72D64300HU-6-B, indicating rev. B dies are used for SDRAM components. The Compliance Code is

printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition

(for example “20330” means CAS latency of 2.0 clocks, RCD (

Row-Column-Delay

) latency of 3 clocks, Row Precharge

latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.

Rev. 1.22, 2007-01

03292006-CXBY-V2JX

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