FM18W08
A second design consideration relates to the level of
V
DD
during operation. Battery-backed SRAMs are
forced to monitor V
DD
in order to switch to battery
backup. They typically block user access below a
certain V
DD
level in order to prevent loading the
battery with current demand from an active SRAM.
The user can be abruptly cut off from access to the
nonvolatile memory in a power down situation with
no warning or indication.
F-RAM memories do not need this system overhead.
The memory will not block access at any V
DD
level
that complies with the specified operating range. The
user should take measures to prevent the processor
from accessing memory when V
DD
is out-of-
tolerance. The common design practice of holding a
processor in reset during powerdown may be
sufficient. It is recommended that Chip Enable is
pulled high and allowed to track V
DD
during powerup
and powerdown cycles. It is the user’s responsibility
to ensure that chip enable is high to prevent accesses
below V
DD
min. (2.7V). Figure 3 shows a pullup
resistor on /CE which will keep the pin high during
power cycles assuming the MCU/MPU pin tri-states
during the reset condition. The pullup resistor value
should be chosen to ensure the /CE pin tracks V
DD
yet
a high enough value that the current drawn when /CE
is low is not an issue.
V
DD
R
FM18W08
CE
MCU/
MPU
WE
OE
A(14:0)
DQ
Figure 3. Use of Pullup Resistor on /CE
Rev. 2.0
Dec. 2011
Page 5 of 11
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