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FM31278_11 参数 Datasheet PDF下载

FM31278_11图片预览
型号: FM31278_11
PDF下载: 下载PDF文件 查看货源
内容描述: 5V集成处理器伴侣与记忆 [5V Integrated Processor Companion with Memory]
分类和应用:
文件页数/大小: 26 页 / 459 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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FM31278/276/274/272 - 5V I2C Companion  
F-RAM  
Array  
2-Wire  
Interface  
A1, A0  
SCL  
LockOut  
SDA  
LockOut  
Special  
Function  
Registers  
RST  
Watchdog  
LV Detect  
RTC Registers  
X1  
S/N  
PFI  
RTC Cal.  
+
RTC  
X2  
1.2V  
-
CAL/PFO  
512Hz  
CNT1  
CNT2  
Event  
Counters  
-
+
2.5V  
VDD  
Switched Power  
VBAK  
Battery Backed  
Nonvolatile  
Figure 1. Block Diagram  
Pin Descriptions  
Pin Name  
Type  
Pin Description  
A0, A1  
Input  
Device select inputs are used to address multiple memories on a serial bus. To select the  
device the address value on the two pins must match the corresponding bits contained in  
the device address. The device select pins are pulled down internally.  
CNT1,  
CNT2  
Input  
Event Counter Inputs: These battery-backed inputs increment counters when an edge is  
detected on the corresponding CNT pin. The polarity is programmable. These pins  
should not be left floating. Tie to ground if these pins are not used.  
CAL/PFO  
X1, X2  
Output In calibration mode, this pin supplies a 512 Hz square-wave output for clock calibration.  
In normal operation, this is the early power-fail output.  
I/O  
32.768 kHz crystal connection. When using an external oscillator, apply the clock to X1  
and a DC mid-level to X2 (see Crystal Oscillator section for suggestions).  
Active low reset output with weak pull-up. Also input for manual reset.  
Serial Data & Address: This is a bi-directional line for the two-wire interface. It is open-  
drain and is intended to be wire-OR‟d with other devices on the two-wire bus. The input  
buffer incorporates a Schmitt trigger for noise immunity and the output driver includes  
slope control for falling edges. A pull-up resistor is required.  
/RST  
SDA  
I/O  
I/O  
SCL  
Input  
Input  
Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the  
part on the falling edge, and in on the rising edge. The SCL input also incorporates a  
Schmitt trigger input for noise immunity.  
Early Power-fail Input: Typically connected to an unregulated power supply to detect an  
early power failure. This pin should not be left floating.  
PFI  
VBAK  
Supply Backup supply voltage: A 3V battery or a large value capacitor. If no backup supply is  
used, this pin should be tied to ground and the VBC bit should be cleared. The trickle  
charger is UL recognized and ensures no excessive current when using a lithium battery.  
Supply Supply Voltage  
VDD  
VSS  
Supply Ground  
Rev. 2.1  
Sept. 2011  
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