FM3135 Integrated RTC/Alarm/FRAM & Embedded Crystal
CALS
CAL.4-0
Calibration Sign: Determines if the calibration adjustment is applied as an addition to or as a subtraction from
the time-base. This bit can be written only when CAL=1. Battery-backed, read/write.
Calibration Code: These five bits control the calibration of the clock. These bits can be written only when
CAL=1. Battery-backed, read/write.
00h
RTC/Alarm Control
D7
LB
D6
AF
D5
CF
D4
POR
D3
AEN
D2
CAL
D1
W
D0
R
LB
AF
CF
POR
AEN
CAL
W
R
Low Battery Flag: If the V
BAK
source drops to a voltage level insufficient to operate the RTC/alarm, this bit
will be set to ‘1’. All registers need to be re-initialized since the battery-backed register values should be
treated as unknown. The user should clear it to ‘0’ when initializing the system. Battery-backed. Read/Write
(internally set, user can clear bit by writing to a ‘0’).
Alarm Flag: This read-only bit is set to 1 when the time/date match the values stored in the alarm registers with
the Match bit(s) = 0. It is cleared when the RTC/Alarm Control register is read. Battery-backed.
Century Overflow Flag: This read-only bit is set to a 1 when the values in the years register overflows from 99
to 00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record
the new century information as needed. This bit is cleared when the RTC/Alarm Control register is read.
Battery-backed.
Power On Reset Flag: When V
DD
drops below V
SW
, the POR bit will be set to ‘1’. Battery-backed.
Read/Write (internally set, user can clear bit by writing to a ‘0’).
Alarm Enable: This bit enables the alarm function. When AEN is set (and CAL cleared), the ACS pin operates
as an active-low alarm and the AF flag function is enabled. The function of the ACS pin is detailed in Table 3.
When AEN is cleared, no new alarm events will occur but the AF flag and ACS pin will not be cleared.
Battery-backed, read/write.
Calibration Mode: When CAL is set to ‘1’, the clock enters calibration mode. When CAL is set to ‘0’, the clock
operates normally, and the ACS pin is controlled by the RTC alarm. Battery-backed, read/write.
Write RTC: Setting the W bit to ‘1’ freezes updates of the user timekeeping registers. The user can then write
them with updated values. Setting the W bit to ‘0’ causes the contents of the time registers to be transferred to
the timekeeping counters. Battery-backed, read/write.
Read RTC: Setting the R bit to ‘1’ copies a static image of the timekeeping core and place it into the user
registers. The user can then read them without concerns over changing values causing system errors. The R bit
going from ‘0’ to ‘1’ causes the timekeeping capture, so the bit must be returned to ‘0’ prior to reading again.
Battery-backed, read/write.
Rev. 1.2
Feb. 2009
Page 11 of 21
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
