FM3135 Integrated RTC/Alarm/FRAM & Embedded Crystal
issues a Start condition. This simultaneously aborts
FM3135 will begin shifting data out from the current
register address on the next clock. Auto-increment
operates for the special function registers as with the
memory address. A current address read for the
registers look exactly like the memory except that the
device ID is different.
the write operation and allows the read command to
be issued with the slave address LSB set to a ‘1’. The
operation is now a read from the current address.
Read operations are illustrated below.
RTC/Alarm Write Operation
All RTC/Alarm writes operate in a similar manner to
memory writes. The distinction is that a different
device ID is used and only one byte address is needed
instead of two. Figure 12 illustrates a single byte
write to the RTC/Alarm.
The FM3135 contains two separate address registers,
one for the memory address and the other for the
register address. This allows the contents of one
address register to be modified without affecting the
current address of the other register. For example,
this would allow an interrupted read to the memory
while still providing fast access to an RTC register. A
subsequent memory read will then continue from the
memory address where it previously left off, without
requiring the load of a new memory address.
However, a write sequence always requires an
address to be supplied.
RTC/Alarm Read Operation
As with writes, a read operation begins with the
Slave Address. To perform a register read, the bus
master supplies a Slave Address with the LSB set to a
‘1’. This indicates that a read operation is requested.
After receiving the complete Slave Address, the
No
Acknowledge
Stop
Start
S
Address
By Master
By FM3130
Slave Address
1
A
Data Byte
Data
1
P
Acknowledge
Figure 9. Current Address Memory Read
No
Acknowledge
Start
S
Address
Acknowledge
A
By Master
Stop
Slave Address
1
A
Data Byte
Data Byte
1
P
By FM3130
Acknowledge
Data
Figure 10. Sequential Memory Read
Start
No
Acknowledge
Address
Start
S
Address
By Master
Stop
S
Slave Address
0
A
Address MSB
A
Address LSB
Acknowledge
A
Slave Address
1
A
Data Byte
Data
1 P
By FM3130
Figure 11. Selective (Random) Memory Read
Rev. 1.2
Feb. 2009
Page 15 of 21
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
