RTL8110S-32/RTL8110S-64
Datasheet
7.7.2.
PCI Clock Specification
T_high
0.6Vcc
0.5Vcc
0.4Vcc
0.3Vcc
0.2Vcc
T_cyc
0.4Vcc, peak-to-peak
(minimum)
T_low
Figure 10.
3.3V Clock Waveform
V_ih
CLK (@ Device #1)
V_il
T_skew
V_test
T_skew
T_skew
CLK (@ Device #2)
V_il
V_ih
V_test
Figure 11.
Clock Skew Diagram
Table 19.
Symbol
Tcyc
Thigh
Tlow
--
--
Tskew
Parameter
CLK Cycle Time
CLK High Time
CLK Low Time
CLK Slew Rate
RST# Slew Rate
CLK Skew
Clock and Reset Specifications
66MHz
Min
15
6
6
1.5
50
Max
30
33MHz
Min
Symbol
30
∞
11
11
1
4
50
-
2
Parameter
ns
ns
ns
V/ns
mV/ns
ns
4
-
1
Integrated Gigabit Ethernet Controller
26
Track ID: JATR-1076-21
Rev. 1.4