M62333P/FP, M62338P/FP
Timing Chart (Model)
<Start condition to slave address bit>
SDA
1
2
3
4
5
6
7
W
A
SCL
D/A
output
Start condition
<Sub address bit>
SDA
1
2
3
4
5
6
7
8
A
SCL
D/A
output
<DAC data bit to stop condition>
SDA
1
2
3
4
5
6
7
8
A
SCL
D/A
output
Stop
condition
•
Start condition
With SCL at High, SDA line goes from High to Low
•
Stop condition
With SCL at High, SDA line goes from Low to High
(Under normal circumstances, SDA is changed when SCL is Low)
•
Acknowledge bit
The receiving IC has to pull down SDA line whenever receive slave data.
(The transmitting IC releases the SDA line just then transmit 8-bit data.)
Digital Data Formats
STA
Slave address
W
A
Sub address 1
A
DAC data 1
A
…………
Sub address 2
A
DAC data 2
A
Sub address n
A
DAC data n
A
STP
REJ03D0865-0400 Rev.4.00 Mar 25, 2008
Page 6 of 9
RENESAS [ RENESAS TECHNOLOGY CORP ]
